It's scary that these things cannot be patched. And this post will probably
result in intel taking down that document saying look now there are now no
holes!!!!
On 6/28/07, Peter Ferrie <pferrie_at_symantec.com> wrote:
>
> > - Basically the MMU simply does not operate as specified/implimented
> > in previous generations of x86 hardware. It is not just buggy, but
> > Intel has gone further and defined "new ways to handle page tables"
> > (see page 58).
>
> I'm not sure about this - I understood it to mean that if you touch a
> table, you have to invalidate the TLB that corresponds to its linear
> address. This was always how Intel CPUs behaved, even the old ones.
> What changed?
>
> > - Some of these bugs are along the lines of "buffer overflow"; where
> > a write-protect or non-execute bit for a page table entry is
> ignored.
>
> Same thing here - altering tables without flushing the TLBs will result in
> cached data being used instead. Intel is documenting it very well now,
> but
> it's not new behaviour.
>
> > Others are floating point instruction non-coherencies, or memory
> > corruptions -- outside of the range of permitted writing for the
> > process -- running common instruction sequences.
>
> The FPU memory corruption is old behaviour, too.
>
> Certainly, there are some scary things in the list, but many of them are
> behaviours that are being documented for the first time, yet they exist
> in CPUs since even the 486, for example.
>
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Received on Jun 28 2007
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