Re: Pentium bug workaround in NetBSD (was Re: Intel Pentium

[robin.hood () ibm net (Edwin Li-Kai Liu)]

Charles M. Hannum wrote:

> Actually, that isn't quite true.  RF is always set when we get the
> page fault.  It turns out there's no way to distinguish a real trace
> trap from an INT 1 or ICEBP/INT01, and that full decoding of the BOUND
> instruction is not necessary because the saved PC points to the BOUND
> instruction itself.  Incorporating only these two changes, the
> processing rules I suggested would be more correctly stated as:

I disagree with the above statement. According to my note regarding INT1,
you can always get the INT1 status by DR6 debug register. The following is
the list of the meaning when these bits are set in DR6 (the note is for 386,
but I think it applies to later chips).

Bits - Reason
------------------------------------------------------
B0   - Breakpoint defined by DR0 is triggered.
B1   - Breakpoint defined by DR1 is triggered.
B2   - ...... by DR2 is triggered.
B3   - ...... by DR3 is triggered.
BD   - Intel ICE hardware is active and ICE is blocking the use of debug
registers.
BS   - Single step (TF is set)
BT   - Task switch (T bit in TSS is set).

This is what the bits look like:

_________________________________________________________________
|                               |B|B|B|                 |B|B|B|B|
|             0                 |T|S|D|        0        |3|2|1|0| DR6
-----------------------------------------------------------------
31                              16                              0

--

Robin Hood
Liu Li-Kai, Edwin

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