Re: Memories (was University credentials used by third parties)

[Valdis Kletnieks <Valdis.Kletnieks () VT EDU>]

On Fri, 20 Aug 2010 13:56:10 PDT, "David L. Wasley" said:

> Then there was the Cray.  I was told the coax
> cabling on the "backplane" had to be cut and
> terminated to within a few mm of each other in
> order that propagation delays would be close
> enough to clock reliably parallel "words". 

Probably refers to this:

"All timing within the mainframe cabinet is controlled by a single phase
synchronous clock network. This clock has a period of 12.5 nsec. The lines that
carry the clock signal from the central clock source to the individual modules
of the CPU are all made of uniform length so that the leading edge of a clock
signal arrives at all parts of the CPU cabinet at the same time. A three
nanosecond pulse (figure 2-3) is formed on each module."

http://ed-thelen.org/comp-hist/CRAY-1-HardRefMan/CRAY-1-HRM.html

However, given that only a few paragraphs above, we have "The high-speed logic
gate has a minimum propagation delay of 0.5 nsec and a maximum propagation
delay of 1 nsec. Edge speeds are 1 nsec or less.", I'm doubtful on the
millimeters story.  The mention of the edge speeds is key here - in general,
you can't rely on detecting a transition in much less than the edge speed, so
that tells us that the design could tolerate on the order of  1ns worth of
timing wonkyness. Now, electricity travels 1 foot per nanosecond, so call it
300mm.    Even assuming a centimeter tolerance, that's still 30 times tighter
than the stuff inside the high-speed logic.  And a few millimeters would be 100
times tighter than the high-speed logic needed.

But "within a few millimeters" does make for a better story than "within a foot or so" ;)

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